View SY89464UMYTR_5534979.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

sy89464u precision lvpecl 1:10 fanout with 2:1 runt pulse eliminator mux and internal termination precision edge is a registered trademark of micrel, inc. micrel inc. ? 2180 fortune drive ? san jose, ca 95131 ? usa ? tel +1 (408) 944 - 0800 ? fax + 1 (408) 474 - 1000 ? http://www.micrel.com december 2007 m9999 - 120607- c hbwhelp@micrel.com or (408) 955 - 1690 general description the sy89464u is a low jitter 1:10 lvpecl fanout buffer with a 2:1 differential input multiplexer (mux) optimized for r e dundant source switchover applications. unlike standard mult i plexers, the sy89464u?s unique 2:1 runt pulse eliminat or (rpe) mux pr e vents any short cycles or ?runt? pulses during switchover. in a d dition, a unique fail - safe input (fsi) protection prevents metastable output conditions when the selected input clock fails to a dc voltage (voltage between the pins of the dif ferential input drops below 100mv). the differential input includes micrel?s unique, 3 - pin internal termination architecture that allows customers to inte r face to any differential signal (ac - or dc - coupled) as small as 100mv (200mv pp ) without any level shi fting or termin a tion resistor networks in the signal path. the ou t puts are 800mv, 100k - compatible lvpecl with fast rise/fall times guaranteed to be less than 220ps. the sy89464u operates from a 2.5v 5% or 3.3v 10% supply and is guaranteed over the full i ndustrial temper a ture range of ? 40c to +85c. the sy89464u is part of micrel?s high - speed, precision edge ? product line. all su p port documentation can be found on m i crel?s web site at: www.micrel.com . precisio n edge ? features ? selects between two sources, and provides 10 precision lvpecl copies ? guaranteed ac performance over temperature and supply voltage: ? wide operating frequency: 1khz to >1.5ghz ? < 1100ps in - to - out t pd ? < 220ps t r /t f ? unique, patent - pen ding mux input isolation design minimizes adjacent channel crosstalk ? fail - safe input prevents oscillations ? ultra - low jitter design: ? <1ps rms random jitter ? <1ps rms cycle - to - cycle jitter ? <10ps pp total jitter (clock) ? <0.7ps rms mux crosstalk induced jit ter ? unique patented internal termination and vt pin accepts dc - and ac - coupled inputs (cml, pecl, lvds) ? 800mv lvpecl output ? 2.5v 5% or 3.3v 10% supply voltage ? output enable ? - 40c to +85c industrial temperature range ? available in 44 - pin (7mm x 7mm) qfn p ackage applications ? redundant clock switchover ? fail - safe clock protection markets ? lan/wan ? enterprise servers ? ate ? test and measurement
micrel, inc. sy89464u december 2 007 m9999 - 120607-b hbwhelp@micrel.com or (408) 955 - 1690 2 typical application simplified example illustrating runt pulse eliminator (rpe) when primary clock fails
micrel, inc. sy89464u december 2 007 m9999 - 120607-b hbwhelp@micrel.com or (408) 955 - 1690 3 ordering information (1) part number package type operating range package marking lead finish sy89464umy qfn -44 indu s trial sy89464u with pb - free bar - line indicator matte -sn pb - free sy89464umy tr (2) qfn -44 indu s trial sy89464u with pb - free bar - line in dicator matte -sn pb - free notes: 1. contact factory for die availability. dice are guaranteed at t a = 25c, dc electricals only. 2. tape and reel. pin configuration 44- pin qfn
micrel, inc. sy89464u december 2 007 m9999 - 120607-b hbwhelp@micrel.com or (408) 955 - 1690 4 pin description pin number pin name pin function 2, 5 7, 10 in0, /in0 in1, /in1 differential inputs: these input pairs are the differential signal inputs to the device. these inputs accept ac - or dc - coupled signals as small as 100mv (200mv pp ). each pin of a pair internally terminates to a v t pin through 50 ? . please refer to the ?input interface applications? section for more details. 4, 9 vref - ac0 vref - ac1 reference voltage: these outputs bias to v cc ? 1.2v. they are used for ac - coupling inputs in and /in. connect v ref - ac directly to the corresponding v t pi n. bypass with 0.01 f low esr capacitor to v cc . due to the limited drive capability, the v ref - ac pin is only intended to drive its respective v t pin. maximum sink/source current is 1.5ma. please refer to the ?input interface applications? section for more details. 3, 8 vt0, vt1 input termination center - tap: each side of the differential input pair terminates to a v t pin. the v t0 and v t1 pins provide a center - tap to a termination network for maximum interface flexibility. please refer to the ?input interfa ce applications? section for more details. 13, 15, 22, 23, 28 33, 34, 41, 43, 44 vcc positive power supply: bypass with 0.1 f || 0.01 f low esr capacitors as close to the v cc pins as possible. 40, 39 38, 37 36, 35 32, 31 30, 29 27, 26 25, 24 21, 20 19, 18 17, 16 q0, /q0 q1, /q1 q2, /q2 q3, /q3 q4, /q4 q5, /q5 q6, /q6 q7, /q7 q8, /q8 q9, /q9 differential outputs: these differential lvpecl outputs are a logic function of the in0, in1, and sel i n puts. please refer to the ?truth table? below for details. 42 sel this single - ended ttl/cmos - compatible input selects the inputs to the multiplexer. note that this input is internally connected to a 25k ? pull - up resistor and will default to logic high state if left open. v th = v cc /2. 1, 6, 11 gnd, exposed pad ground: ground and exposed pad must be connected to the same ground plane. 12 cap power - on reset (por) initialization capacitor. when using the multiplexer with rpe capability, this pin is tied to a capacitor to v cc . the purpose is to ensure the internal rpe log ic starts up in a known state. see ?power - on reset (por) description? section for more d e tails regarding capacitor selection. if this pin is tied directly to v cc , the rpe function will be disabled and the multiplexer will function as a normal multiplexer. the cap pin should never be left open or tied directly to gnd. 14 en single - ended input: this ttl/cmos input disables and enables the q0- q9 outputs. it is internally connected to a 25k ? pull - up resistor and will default to a logic high state if left open. when disabled, clk output goes low and /clk goes high. en being synchronous, outputs will be enabled/disabled when they are in low state. thus, a runt pulse is avoided if the device is enable/disabled by an asynchronous control. v th = v cc /2. truth table inputs outputs in0 /in0 in1 /in1 sel q /q 0 1 x x 0 0 1 1 0 x x 0 1 0 x x 0 1 1 0 1 x x 1 0 1 1 0
micrel, inc. sy89464u december 2 007 m9999 - 120607-b hbwhelp@micrel.com or (408) 955 - 1690 5 absolute maximum ratings (1) supply voltage (v cc ) .......................... ? 0.5v to +4.0v input voltage (v in ) .................................. ? 0.5v to v cc lvpecl output current (i out ) .................................... continuous ................................................. 50ma surge ........................................................ 100ma input current (i in ) ........................................................ in, /in ....................................................... 50ma v t ............................................................ 100ma v ref-ac current source/sink current on v ref -ac .................. 2ma lead temperature (soldering, 20 sec.) .......... +260c storage temperature (t s ) .................. ? 65c to 150c operating ratings (2) supply voltage (v cc ) .................. +2.375v to +2.625v ...................................................... +3.0v to +3.6v ambient temperature (t a ) ................ ? 40c to +85c package thermal resistance (3) qfn ( ja ) still - air .................................................. 24.4c/w qfn ( jb ) junction - to - board ................................... 8.1c/w dc electrical characteristics (4) t a = ? 40c to +85c, unless otherwise stated. symbol parameter condition min typ max units v cc power supply 2.375 3.0 2.5 3.3 2.625 3.6 v v i cc power su pply current no load, max v cc 120 160 ma r in input resistance (in -to -v t ) 45 50 55 ? r diff_in differential input resistance (in -to - /in) 90 100 110 ? v ih input high voltage (in, /in) 1.2 v cc v v il input low voltage (in, /in) 0 v ih ? 0.1 v v in input voltage swing (in, /in) see figure 1a. note 5. 0.1 2.5 v v diff_in differential input voltage swing |in - /in| see figure 1b. 0.2 v v in_fsi input voltage threshold that triggers fsi 30 100 mv v t_in in -to -v t (in, /in) 1.28 v v ref - ac output referen ce voltage v cc ? 1.3 v cc ? 1.2 v cc ? 1.1 v notes: 1. permanent device damage may occur if absolute maximum ratings are exceeded. this is a stress rating only and fun c tional operation is not implied at conditions other than those detailed in the operational sec tions of this data sheet. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. the data sheet limits are not guaranteed if the device is operated beyond the operating ratings. 3. package thermal resistance a ssumes exposed pad is soldered (or equivalent) to the devices most negative potential on the pcb. ja and jb values are determined for a 4 - layer board in still air unless otherwise stated. 4. the circuit is designed to meet the dc specifications shown in the above table after thermal equilibrium has been established . 5. v in (max) is specified when v t is floating.
micrel, inc. sy89464u december 2 007 m9999 - 120607-b hbwhelp@micrel.com or (408) 955 - 1690 6 lvpecl outputs dc electrical characteristics (6) v cc = 2.5v 5% or 3.3v 10%; r l = 50 ? to v cc - 2v; t a = ? 40c to + 85c, unless otherwise stated. symbol parameter condition min typ max units v oh output high voltage q, /q v cc - 1.145 v cc - 0.895 v v ol output low voltage q, /q v cc - 1.945 v cc - 1.695 v out output voltage swing q, /q see figure 1a. 550 800 mv v diff_out differential output voltage swing q, /q see figure 1b. 1100 1600 mv lvttl/cmos dc electrical characteristics (6) v cc = 2.5v 5% or 3.3v 10%; t a = ? 40c to + 85c, unless otherwise stated. symbol parameter condition min typ max units v ih input high voltage 2.0 v v il input low voltage 0.8 v i ih input high current -125 30 a i il input low current -300 a note: 6. the circuit is designed to meet the dc specifications shown in the above table after thermal equilibrium has been established.
micrel, inc. sy89464u december 2 007 m9999 - 120607-b hbwhelp@micrel.com or (408) 955 - 1690 7 ac electrical characteristics (7) v cc = 2.5v 5% or 3.3v 10%; r l = 50 ? to v cc - 2v; t a = ? 40c to + 85c, unless otherwise stated. sym bol parameter condition min typ max units f max maximum operating frequency v out 400mv 1.5 2.0 ghz t pd differential propagation delay in -to -q 100mv < v in 200mv (8) 550 800 1150 ps in -to -q 200mv < v in 800mv (8) 500 750 1100 ps sel -to -q rpe enabled, see timing diagram 17 cycles sel -to -q rpe disabled (v sel = v cc /2) 600 1200 ps t pd tempco differential propagation delay te m perature coefficient 500 fs/ o c t s en set - up time en -to - clk note 9 0 ps t h en hold time clk -to -en no te 9 650 ps t skew output -to - output skew note 10 5 25 ps part -to - part skew note 11 300 ps t jitter clock random jitter note 12 1 ps rms cycle -to - cycle jitter note 13 1 ps rms total jitter note 14 10 ps pp crosstalk - induced j itter note 15 0.7 ps rms t r, t f output rise/fall time (20% to 80%) at full output swing. 70 220 ps notes: 7. high - frequency ac - parameters are guaranteed by design and characterization. 8. propagation delay is measured with input t r , t f 300ps (20% to 80%) and v il 800mv. the propagation delay is function of the rise and fall times at in. see ?typical operating characteristics? for details. 9. set - up and hold times apply to synchronous applications that intend to enable/disable before the next clock c ycle. for asynchronous applications, set - up and hold do not apply. 10. output - to - output skew is measured between two different outputs under identical transitions. 11. part - to - part skew is defined for two parts with identical power supply voltages at the s ame temperature and with no skew of the edges at the respective inputs. 12. random jitter is measured with a k28.7 character pattern, measured at micrel, inc. sy89464u december 2 007 m9999 - 120607-b hbwhelp@micrel.com or (408) 955 - 1690 8 functional description rpe mux and fail - safe input the sy89464u is optimized for clo ck switchover applications where switching from one clock to a n other clock without runt pulses (short cycles) is r e quired. it features two unique circuits: runt - pulse eliminator (rpe) circuit the rpe mux provides a ?glitchless? switchover between two clock s and prevents any runt pulses from occurring during the switchover transition. the design of both clock inputs is identical (i.e., the switchover sequence and protection is symmetrical for both input pairs, in0 or in1. thus, either input pair may be defin ed as the primary input). if not r e quired, the rpe function can be permanently di s abled to allow the switchover between inputs to o c cur immediately. if the cap pin is tied directly to v cc , the rpe function will be disabled and the multiplexer will function as a normal multiplexer. fail - safe input (fsi) circuit the fsi function provides protection against a selected input pair that drops below the minimum amplitude requirement. if the s e lected input pair drops sufficiently below the 100mv minimum si n gle - ende d input amplitude limit (v in ), or 200mv di f ferentially (v diff_in ), then the output will latch to the last valid clock state. rpe and fsi functionality the basic operation of the rpe mux and fsi functionality is described with the following four case de scriptions. all descriptions are related to the true inputs and outputs. the primary (or selected) clock is called clk1; the secondary (or alternate) clock is called clk2. due to the totally asynchr o nous relation of the in and sel signals, and an a d ditiona l internal prote c tion against metastability, the number of pulses required for the operations d e scribed in cases 1 - 4 can vary within certain li m its. refer to ?timing di a grams? section for detailed inform a tion. case #1: two normal clocks and rpe - enabled in this case, the frequency difference between the two running clocks, in0 and in1, must not be greater than 1.5:1. for example, if the in0 clock is 500mhz, the in1 clock must be within the range of 334mhz to 750mhz. if the sel input changes state to select the a l ternate clock, the switchover from clk1 to clk2 will occur in three stages. ? stage 1: the output will continue to follow clk1 for a limited number of pulses. ? stage 2: the output will remain low for a limited number of pulses of clk2. ? stage 3: t he output follows clk2. timing diagram 1
micrel, inc. sy89464u december 2 007 m9999 - 120607-b hbwhelp@micrel.com or (408) 955 - 1690 9 case #2: input clock failure: switching from a s e lected clock stuck high to a valid clock (rpe - e n abled). if clk1 fails high before the rpe mux selects clk2 (using the sel pin), the switchover will occur in t hree stages. ? stage 1: the output will remain high for a lim ited number of pulses of clk2. ? stage 2: the output will switch to low and then remain low for a limited number of fa l ling edges of clk2. ? stage 3: the output will follow clk2. timing dia gram 2 note: output shows extended clock cycle during switchover. pulse width for both high and low of this cycle will always be greater than 50% of the clk2 period.
micrel, inc. sy89464u december 2 007 m9999 - 120607-b hbwhelp@micrel.com or (408) 955 - 1690 10 case #3: input clock failure: switching from a selected clock stuck low to a val id clock (rpe - enabled). if clk1 fails low before the rpe mux selects clk2 (using the sel pin), the switchover will occur in two stages. ? stage 1: the output will remain low for a limited number of falling edges of clk2. ? stage 2: the output will follow cl k2. timing diagram 3
micrel, inc. sy89464u december 2 007 m9999 - 120607-b hbwhelp@micrel.com or (408) 955 - 1690 11 case #4: input clock failure: switching from the selected clock input stuck in an undetermined state to a valid clock input (rpe - enabled). if clk1 fails to an undetermined state (e.g., amplitude falls below the 100mv (v in ) minim um single - ended input limit, or 200mv differentially) before the rpe mux selects clk2 (using the sel pin), the switchover to the valid clock clk2 will occur either following case #2 or case #3, depending upon the last valid state at the clk1. if the selec ted input clock fails to a floating, static, or extremely low signal swing, including 0mv, the fsi function will eliminate any metastable condition and guarantee a stable output signal. no ringing and no undetermined state will occur at the output under th ese conditions. please note that the fsi function will not prevent duty cycle distortions or runt pulses in case of a slowly deteriorating (but still toggling) input signal. due to the fsi function, the propagation delay will depend upon rise and fall time of the input signal and on its amplitude. refer to ?typical operating characteristics? for detailed information. timing diagram 4
micrel, inc. sy89464u december 2 007 m9999 - 120607-b hbwhelp@micrel.com or (408) 955 - 1690 12 enable output (en) description the enable function is synchronous so that the outputs will be enabled/disab led when they are already in the low state. this avoids any chance of generating a runt pulse when the device is enabled/disabled as can happen with asynchronous control. disable output(s): 1. en toggles from high - to - low 2. output(s) follow the selected clock i nput 3. output (clk) goes to a logic low level (/clk goes to a logic high), after next high - to - low transition of the selected input. see timing diagram 5. enable output(s): 1. en toggles from low - to - high. 2. output(s) follow the selected clock after next high - to - l ow transition of the selected input. see ?timing diagram 5.? timing diagram 5
micrel, inc. sy89464u december 2 007 m9999 - 120607-b hbwhelp@micrel.com or (408) 955 - 1690 13 power - on reset (por) description the sy89464u includes an internal power - on r e set (por) function to ensure the rpe logic starts - up in a known logic state once the pow er - supply voltage is stable. an external capacitor co n nected between v cc and the cap pin (pin 12) co n trols the delay for the power - on reset function. the required capac i tor value calculation is based upon the time the system power supply needs to power up to a minimum of 2.3v. the time constant for the internal power - on- reset must be greater than the time required for the power supply to ramp up to a minimum of 2.3v. the following formula describes this relationship: c( f) t dps (m s) 12(ms / f) as an example, if the time required for the system power supply to power up past 2.3v is 12ms, then the r e quired capacitor value on pin 12 would be: c( f) 12 ms 12 (m s / f) c( f) ??)
micrel, inc. sy89464u december 2 007 m9999 - 120607-b hbwhelp@micrel.com or (408) 955 - 1690 14 typical operating characteristics v cc = 3.3v, gnd = 0v, t r / t f 300ps, r l = 50 ? to v cc ? 2v; t a = 25c, unless otherwise stated.
micrel, inc. sy89464u december 2 007 m9999 - 120607-b hbwhelp@micrel.com or (408) 955 - 1690 15 functional characteristics v cc = 2.5v, gnd = 0v, v in 400mv pk , t r /t f 300ps, r l = 50 ? to v cc - 2v; t a = 25c, unless otherwise stated.
micrel, inc. sy89464u december 2 007 m9999 - 120607-b hbwhelp@micrel.com or (408) 955 - 1690 16 single- ended and differential swings figure 1a. single - ended voltage swing figure 1b. differential voltage swing input and output stages figure 2a. simplified differential input stage figure 2b. simplified differential output stage
micrel, inc. sy89464u december 2 007 m9999 - 120607-b hbwhelp@micrel.com or (408) 955 - 1690 17 input interface applications figure 3a. lvpecl interface (dc - coupled) figure 3b. lvpecl interface (ac - coupled) option: may connect v t to v cc figure 3c. cml interface (dc - coupled) figure 3d. cml interfa ce (ac - coupled) figure 3e. lvds interface (dc - coupled)
micrel, inc. sy89464u december 2 007 m9999 - 120607-b hbwhelp@micrel.com or (408) 955 - 1690 18 pecl output interface applications pecl has a high input impedance, a very low output impedance (open emitter), and a small signal swing which results in low emi. pecl is ideal for driving 50? - and 100 ? - controlled impedance transmission lines. there are several techniques for terminating the pecl output: parallel termination - thevenin equivalent, parallel termination (3 - resistor), and ac - coupled termination. unused output pairs may be left flo ating. however, single - ended outputs must be terminated, or balanced. figure 4a. parallel termination - thevenin equivalent figure 4b. parallel termination (3 - resistor) related product and support documentation part number function data sheet link sy89465u precision lvds runt pulse eliminator 2 :1 mux with 1:10 fanout buffer and internal termination www.micrel.com/product - info/products/sy89465u.shtml . hbw solut ions new products and applications www.micrel.com/product - info/products/solutions.shtml
micrel, inc. sy89464u december 2 007 m9999 - 120607-b hbwhelp@micrel.com or (408) 955 - 1690 19 44 -pin qfn packages notes: 1. package meets level 2 moisture sensitivity classificati on. 2. all parts are dry - packed before shipment. 3. exposed pad must be soldered to a ground for proper thermal management. micrel, inc. 2180 fortune drive san jose, ca 95131 usa tel +1 (408) 944 - 0800 fax +1 (408) 474 - 1000 web http:/www.micrel.com the information furnished by micrel in this data sheet is believed to be accurate and reliable. however, no responsibility is assumed by micrel for its use. micrel reserves the right to change circuitry and specifications at any time without notification to the custome r. micrel products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) su pport or sus tain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. a purchaser?s use or sale of micrel products for use in life support appliances, devices or s ystems is a purchaser?s own risk and purchaser ag rees to fully indemnify micrel for any damages resulting from such use or sale. ? 2005 micrel, inc.

▲Up To Search▲

Price & Availability of SY89464UMYTR

	To Download SY89464UMYTR Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .